De-emphasis system and method for coupling digital signals through capacitively loaded lines

ABSTRACT

A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/113,066, filed Apr. 30, 2008, which is a divisional of U.S. patentapplication Ser. No. 11/442,510, filed May 25, 2006, U.S. Pat. No.7,375,573. These applications are incorporated by reference herein.

TECHNICAL FIELD

This invention relates to digital integrated circuits, and, moreparticularly, to a system and method for adjusting the waveform of adigital signal before it is coupled though a highly capacitive line tomake it easier to correctly detect the signal at a receiving device.

BACKGROUND OF THE INVENTION

As the operating speeds of electronic devices, such as memory devices,continues to increase, the timing of digital signals received by thedevices has become ever more critical. For example, in a memory device,such as a dynamic random access memory (“DRAM”) device, command, addressand write data signals are transmitted to the memory device by a memorycontroller, and read data signals are transmitted to the memorycontroller by the memory device. Conventional memory devices generallyoperate synchronously with a clock signal, which defines the times thatthe received signals are considered valid. As the operating speed ofmemory devices continues to increase, the period during which thecommand, address and write data signals received by the memory deviceare considered valid has become ever shorter. As a result, it has becomemore critical to control the timing at which these signal are receivedby memory devices.

The timing of digital signals, such as command, address and datasignals, are adversely affected by “jitter,” which is high frequencyphase noise that cause rapid changes in the timing at which transitionsof the digital signal occur. Jitter can be caused by a number ofsources, such as noise coupled to digital circuits along with a digitalsignal, which causes the switching time of the digital circuit to varyin a random manner. Jitter can also be caused by variations in the shapeof digital signals coupled to digital circuits.

With reference to FIG. 1, a digital signal having the waveform shown bythe dotted line may be applied into a signal line. When the digitalsignal is applied to the signal line, its signal levels vary betweenvoltages 0 and V*. As shown in FIG. 1, the transmitted waveform has a50% duty cycle between time t₀ and time t₂. A “double width” pulse thenoccurs starting at time t₂ followed by a return to the original waveformstarting at time t₄. If the signal line is highly capacitive, thewaveform received by a downstream electronic device may have thewaveform shown by the solid line in FIG. 1. As a result of thecombination of the high frequency of the signal and the high capacitanceof the signal line, the received waveform never reaches the fullamplitudes of the transmitted waveform. For example, the transmittedsignal starts charging the capacitive signal line toward the voltage V*at time t₀, which is shown by the dotted arrow at time t₀. However, theamplitude of the received signal never reaches the level V* volts.Instead, it reaches the level V₁ at time t₁, at which time thetransmitted signal starts discharging the signal line toward 0 volts, asagain shown by the dotted arrow. Again, the amplitude of the receivedsignal never reaches 0 volts. Instead, it reaches the level V₂ at timet₂, at which time the transmitted signal again starts charging thesignal line. Thus, the capacitive signal line charges toward V* voltsfrom V₂ volts, and it starts discharging toward 0 volts from V₁ volts.

The symmetrical, unvarying shape of the transmitted signal between timest₀-t₂, causes the received signal to cross the midpoint voltage M withthe same delay after each corresponding edge of the transmitted signal.This can be seen by the uniform spacing between the dotted arrows andthe immediately following solid arrows. As a result, a digital circuitthat switches state at the midpoint voltage M will change state with auniform delay after each transition of the signal applied to the signalline.

During the double width pulse starting at time t₂, the signal line ischarged toward the voltage V* for a longer period of time. The receivedsignal therefore reaches the amplitude V₃ volts at time 4 at which timethe signal line begins being discharged toward 0 volts. The receivedsignal still crosses the midpoint voltage M with the same delay afterthe corresponding edge of the transmitted signal as shown by the solidarrow following the dotted arrow at time t₂. However, because thedischarge of the signal line starts from V₃ volts rather than the loweramplitude of V₁ volts, it now crosses the midpoint voltage M with a muchlonger delay after the corresponding edge of the transmitted signal. Theskew of the received signal can be seen by the increased spacing of thesolid arrow immediately following the dotted arrow at time t₄. This skewin the midpoint amplitude M crossing delay as function of the bitpattern of the transmitted signal can results in signal jitter at acircuit receiving the signal. As explained above, jitter can adverselyaffect the receiving circuit's ability to capture the correct pattern ofthe transmitted digital signal because the receiving circuit mayregister the incorrect bit from the received signal.

This jitter problem is particularly acute in coupling address signal tomemory devices. Address signal are typically transmitted to a pluralityof memory devices through a signal distribution tree. The relativelylarge size of the tree when a large number of memory devices are presentmakes the address lines highly capacitive. In fact, the jitter caused bythe high capacitance of address signal trees can defeat the major reasonfor using a tree, i.e., to ensure that address signal transitions arriveat all of the memory devices at the same time. The memory devices in asystem attempt to capture the address signals using a clock signal,which may also be coupled through a clock tree. Ideally, a transition ofthe clock signal used to capture the address signals occurs at thecenter of the address signal. However, jitter can cause timing skewsthat cause the clock signal transition to occur before or after a“window” or “eye” during which the address signals are valid. Forexample, as shown in FIG. 2, if a clock signal CLK does not cause eachof several address signals A<0:9> to latch at the proper time, errors inthe operation of the memory device may result. Thus, the timing skew ofthe clock signal CLK relative to the timing skews of the address signalsA<0:9> must be limited to allow the CLK signal to latch each of theseveral address signals A<0:9>. As the data transfer rate increases, theduration of each eye E for which each address signal A<0>-A<9> is validdecreases by a corresponding amount, as will be understood by oneskilled in the art. With further reference to FIG. 2, the solid linesindicate the ideal address signals A<0>, A<1>, and A<9> signals, and thedashed lines indicate the worst case potential time skew for each ofthese signals. The ideal address signals A<0>, A<1>, and A<9> arecentered at the rising edge of the CLK signals. The eyes E during whichthe address signals A<0>, A<1>, and A<9> are valid are defined by timeintervals t₀-t₃, t₁-t₄, and t₅-t₇, respectively. In fact, the eyes E ofthe applied address signals A<0>-A<9> may even vary to such an extentthat not all of the address signals are simultaneously valid at anytime. In other words, there is no time during which the eyes E of all ofthe address signals overlap. Under these circumstances, the idealaddress signals A<0>, A<1>, and A<9> signals, all of the address signalsA<0>-A<9> cannot possibly be captured by the CLK signal. For example, inFIG. 2, the eye E of the A<0> signal from times t₀-t₃ does not overlapthe eye of the A<9> signal from times t₅-t₇. It is therefore importantto limit the jitter or timing skew of the CLK and address signalsA<0>-A<9>.

Attempts have been made to solve the jitter problem exemplified by FIGS.1 and 2 using various equalization techniques. Two differentequalization approaches have been tried. The first approach attempts tomodify the characteristics of the signal line by either making it lesscapacitive or by making a transmitted signal less affected by thecapacitance, such as by inserting repeaters or inverters in the line.Unfortunately, this approach can unduly increase the cost of digitaldevices. The second approach attempts to modify the shape of thetransmitted signal so that the capacitance of the signal line causes itto be received with close to its original shape. In one example, everytransition of the digital signal is provided with a large overshoot,which is capacitively filtered out by the signal line. The size andcomplexity of circuitry using this approach can again unduly increasethe cost of digital devices, particularly since the nature of themodification must depend on the characteristics of the bit pattern.

There is therefore a need for a relatively inexpensive system and methodfor allowing digital signals having an irregular bit pattern to becoupled through highly capacitive signal lines without causing jitter inthe received signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a timing diagram illustrating the manner in which signaljitter is created by coupling a digital signal through a highlycapacitive signal line.

FIG. 2 is a timing diagram showing the manner in which timing skew orjitter can prevent a clock signal from capturing address signals duringan “eye” when the address signals are valid.

FIGS. 3A and 3B are timing diagrams illustrating the manner in whichsignal jitter is avoided by a signal de-emphasis system and methodaccording to one example of the invention.

FIG. 4 is a block diagram of a de-emphasis system according to oneexample of the invention.

FIG. 5 is a block diagram of a computer system using the de-emphasissystem shown in FIG. 4 or a de-emphasis system according to some otherexample of the invention.

DETAILED DESCRIPTION

The manner in which a signal de-emphasis system and method according toone example of the invention avoids creating signal jitter is shown inFIGS. 3A and 3B. A digital signal that is to be transmitted through ahighly capacitive signal line is shown in FIG. 3A. The signal is assumedto be referenced to a clock signal (not shown) that may be transmittedalong with the signal. The signal is high for one clock period betweentimes t₀ and t₁, is then low for one clock period between times t₁ andt₂, is high for three clock periods between times t₂ and t₅, low for oneclock period between times t₅ and t₆, then high for one clock periodbetween times t₆ and t₇, and finally low for two clock periods betweentimes t₇ and t₉.

The de-emphasis system and method applies the digital signal to thesignal line with the shape shown by the solid line in FIG. 3. As showntherein, when the digital signal is high, it is applied to the signalline with a level of V* volts for the first period of the clock signal,and it then transitions to V₁ volts for any remaining period of theclock signal. Similarly, when the digital signal is low, it is appliedto the signal line with a level of 0 volts for the first period of theclock signal, and it then transitions to V₂ volts for any remainingperiod of the clock signal. Thus, when the digital signal is high forthree clock periods between times t₂ and t₅, it is applied to the signalline as V* volts for the first clock period between times t₂ and t₃followed by V₁ volts for the remaining two clock periods between timest₃ and t₅. When the digital signal is low for two clock periods betweentimes t₇ and t₉, it is applied to the signal line as 0 volts for thefirst clock period between times t₇ and t₈ followed by V₂ volts for theremaining clock period between times t₈ and t₉.

The digital signal as it is received from the highly capacitive signalline at a downstream location is shown by the dotted line in FIG. 3B.The signal line charges toward V* volts between times t₀ and t₁, andreaches approximately V₁ volts after one clock period at time t₁. Thedigital signal is low during the next clock period between times t₁ andt₂, so the signal line begins discharging from V₁ volts toward 0 volts,and it reaches approximately V₂ volts after one clock period at time t₂.The signal line then begins charging from V₂ volts toward V* volts attime t₂. Therefore, the charging of the signal line always starts fromV₂ volts, and the discharging of the signal line always starts from V₁volts.

If the digital signal applied to the signal line is high for more thanone clock period, e.g., between times t₂ and t₅, the signal line isagain charged to voltage V₁ during the first clock period from times t₂and t₃. However, during the next two clock periods between times t₃ andt₅, the signal line remains at V₁ volts because the digital signalapplied to the signal line transitions from V* volts to V₁ volts afterone clock period at time t₃. Therefore, the signal line always startsdischarging from V₁ volts regardless of the number of clock period thedigital signal is high. Similarly, when the signal line beginsdischarging from V₁ volts toward 0 Volts at time t₇, it again reachesapproximately V₂ volts after one clock period at time t₈. During thenext clock period between times t₈ and t₉, the signal line remains at V₂volts because the digital signal applied to the signal line transitionsfrom 0 volts to V₂ volts after one clock period at time t₈. Therefore,the signal line always starts charging from V₂ volts regardless of thenumber of clock period the digital signal is low. It can therefore beseen that the voltages between which the signal line is charged anddischarged is the same regardless of the pattern of the digital signalapplied to the signal line. For this reason, signal jitter of the typeexemplified by FIGS. 1 and 2 does not occur.

A de-emphasis system 10 according to one example of the invention isshown in FIG. 4. The digital signal to be transmitted is applied to aninput terminal 14 and is routed through two signal paths 16, 18. Thefirst signal path 16 includes a multiplier 20 that multiples the digitalsignal by 1-D₁, where D₁ is the change in the digital signal after thefirst clock period that the signal remains high. In the example shown inFIG. 3, D₁ is equal to V*−V₁. For example, if D₁=0.25, the multiplier 20multiplies the digital signal by 0.75. Therefore, if the digital signaltransitions between 0 and 1 volts, the signal at the output of themultiplier 20 will transition between 0 and 0.75 volts.

The second signal path 18 includes a delay circuit 24 followed by asecond multiplier 26. The delay circuit 24 delays the digital signalapplied to the input terminal 14 by one clock period. The multiplier 26multiples the digital signal by D₂, where D₂ is the change in thedigital signal after the first clock period that the signal remains low.Although D₂ need not be equal to D₁, it will be assumed for purposes ofillustration that such is the case. In the example shown in FIG. 3, D₂is equal to V₂. If D₂ is also equal to 0.25, the multiplier willmultiply the digital signal by 0.25.

The respective outputs of the multipliers 20, 26 are applied to adifferential adder 30 that subtracts the output of the second multiplier26 from the output of the first multiplier 20. The resulting output isapplied to a level translator circuit 34. The level translator circuit34 adds a fixed offset to the signal at the output of the adder 30,which, for purposes of illustration is presumed to be equal to D, whereD=D₁=D₂. The voltage levels present in the de-emphasis circuit 10referenced by the letters shown in FIG. 4 for the digital signal shownin FIG. 3 in which D₁=D₂=0.25 are as follows

TABLE 1 Time A B C D E F t0 1 0.75 0 0 0 1 0.25 −0.25 0 1 0.75 0 0 0.751 1 0.75 1 0.25 0.5 0.75 1 0.75 1 0.25 0.5 0.75 0 0 1 0.25 −0.25 0 10.75 0 0 0.75 1 0 0 1 0.25 −0.25 0 0 0 0 0 0 0.25 1 0.75 0 0 0.75 1

It can be seen that column “F” of Table 1 corresponds to the voltagelevels shown in the solid line in FIG. 3.

A computer system 50 using the de-emphasis system 10 shown in FIG. 4 isshown in FIG. 5. The computer system 50 includes a processor 52 forperforming various computing functions, such as executing specificsoftware to perform specific calculations or tasks. The processor 52includes a processor bus 54 that normally includes an address bus, acontrol bus, and a data bus. In addition, the computer system 50includes one or more input devices 54, such as a keyboard or a mouse,coupled to the processor 52 to allow an operator to interface with thecomputer system 50. Typically, the computer system 50 also includes oneor more output devices 56 coupled to the processor 52, such outputdevices typically being a printer or a video terminal. One or more datastorage devices 58 are also typically coupled to the processor 52 toallow the processor 52 to store data in or retrieve data from internalor external storage media (not shown). Examples of typical storagedevices 58 include hard and floppy disks, tape cassettes, and compactdisk read-only memories (CD-ROMs). The processor 52 is also typicallycoupled to cache memory 66, which is usually static random access memory(“SRAM”).

The computer system 50 also includes system memory 70, which is in theform of several registered double in-line memory modules (“DIMMs”) 74.Each of the DIMMs 74 includes a register 76 coupled to several dynamicrandom access memory (“DRAM”) devices 78 by a system of buses 80 thatincludes a command bus, an address bus and a data bus. The registers 76each include a respective de-emphasis system 84 coupled to each of theaddress bus signals lines, which couple addresses to the DRAM devices78. The de-emphasis system 84 may also be coupled to each of the commandbus lines, which transmit memory commands to the DRAM devices 78.Finally, the de-emphasis system 84 may be coupled to each of the databus lines, which transmit write data to the DRAM devices 78. Therefore,even though the signal lines of the buses 80 may be highly capacitive,the signals are transmitted from the registers 76 to the DRAM devices 78with very low signal jitter.

Each of the DIMMs 74 is coupled to a memory controller 90, which isconnected to the processor 52 through the processor bus 54. The DIMMs 74are coupled to the memory controller 90 by a system of buses 92 thatagain includes a command bus, an address bus and a data bus. The memorycontroller 90 includes a de-emphasis system 94 coupled to each of theaddress bus signals lines for transmitted addresses to the DIMMs 74 withrelatively low jitter. The de-emphasis system 94 may also be coupled toeach of the command bus lines and the data bus lines for transmittingmemory commands and write data, respectively, to the DIMMs 74 withrelatively low jitter.

Although the present invention has been described with reference to thedisclosed embodiments, persons skilled in the art will recognize thatchanges may be made in form and detail without departing from the spiritand scope of the invention. Such modifications are well within the skillof those ordinarily skilled in the art. Accordingly, the invention isnot limited except as by the appended claims.

1. (canceled) 2-34. (canceled)
 35. A processor-based system, comprisinga system processor having a processor bus; a system memory operable tostore write data and to retrieve read data at locations correspondingreceived address signals responsive to memory commands; and a systemcontroller coupled to the system processor through the processor bus,the system controller being coupled to the system memory and beingoperable to supply to the system memory a memory signal corresponding toeither a first logic level or a second logic level, the systemcontroller including a de-emphasis system configured to de-emphasize thememory signal before transmitting the memory signal to the systemmemory, the de-emphasis system having an input coupled to receive thememory signal and being configured to generate a de-emphasized memorysignal that is supplied to the system memory, the de-emphasized memorysignal corresponding to a transition from the first logic level to thesecond logic level having a first signal level for a first periodfollowed by a second signal level for as long as the memory signalcorresponds to the second logic level.
 36. The processor-based system ofclaim 35 wherein the de-emphasized memory signal comprises ade-emphasized address signal.
 37. The processor-based system of claim 35wherein the de-emphasized memory signal comprises a de-emphasizedcommand signal.
 38. The processor-based system of claim 35 wherein thede-emphasis system is further configured to generate a de-emphasizedmemory signal that corresponds to a transition from the second logiclevel to the first logic level having a third signal level for a secondperiod followed by a fourth signal level for as long as the memorysignal corresponds to the first logic level.
 39. The processor-basedsystem of claim 38 wherein the first and second periods aresubstantially equal to each other.
 40. The processor-based system ofclaim 39 wherein the de-emphasis system comprises: a delay circuitreceiving a digital signal having either the first logic level or thesecond logic level and being configured to generate a delayed memorysignal at an output terminal having a delay relative to the memorysignal that is equal to the first period responsive to a transition ofthe digital signal from the first logic level to the second logic leveland is equal to a second period responsive to a transition of thedigital signal from the second logic level to the first logic level; afirst multiplier circuit that is operable to generate a firstintermediate signal by multiplying the magnitude of the delayed memorysignal by a first multiplier, a second multiplier circuit that isoperable to generate second intermediate signals by multiplying themagnitude of the delayed memory signal by a second multiplier; and acombining circuit coupled to receive the first and second intermediatesignals to generate de-emphasized memory signal for transmission to thesystem memory by combining the first and second intermediate signals.41. The processor-based system of claim 40 wherein the first multipliercomprises 1-X and the second multiplier comprises X where X is a valueless than
 1. 42. The processor-based system of claim 40 wherein thememory signal is synchronized to a clock signal, and wherein the firstand second delays are substantially equal to one period of the clocksignal.
 43. The processor-based system of claim 38 wherein the magnitudeof the third signal level is substantially equal to the magnitude of thefirst logic level.
 44. The processor-based system of claim 38 whereinthe duration of the first period is equal to the duration of the secondperiod.
 45. The processor-based system of claim 38 wherein the magnitudeof the third signal level is substantially equal to the magnitude of thefirst logic level, and wherein the magnitude of the first signal levelis substantially equal to the magnitude of the second logic level. 46.The processor-based system of claim 38 wherein the magnitudes of thesecond and fourth signal levels are intermediate the magnitudes of thefirst and third signal levels.
 47. The processor-based system of claim38 wherein the magnitude of the first signal level is substantiallyequal to the magnitude of the second logic level.
 48. A processor-basedsystem, comprising a system processor having a processor bus; a systemmemory operable to store write data and to retrieve read data atlocations corresponding received address signals responsive to memorycommands; and a system controller coupled to the system processorthrough the processor bus, the system controller being coupled to thesystem memory and including a de-emphasis system configured to generatea de-emphasized memory signal corresponding to a digital signal havingfirst and second logic level and to transmit the de-emphasized memorysignal to the system memory, the de-emphasis system being responsive tothe digital signal transitioning from the first logic level to thesecond logic level to cause the de-emphasized memory signal to initiallyovershoot a first signal level and then remain at the first signal levelfor as long as the digital signal is at the second logic level.
 49. Theprocessor-based system of claim 48 wherein the de-emphasis system isfurther responsive to the digital signal transitioning from the secondlogic level to the first logic level to cause the de-emphasized memorysignal to initially overshoot a second signal level and then remain atthe second signal level for as long as the digital signal is at thefirst logic level.
 50. The processor-based system of claim 49 whereinthe magnitude of the second signal level is substantially equal to themagnitude of the first logic level.
 51. The processor-based system ofclaim 49 wherein the de-emphasized signal overshoots the first signallevel for a first period and overshoots the second signal level for asecond period that is substantially equal to the first period.
 52. Theprocessor-based system of claim 48 wherein the magnitude of the firstsignal level is substantially equal to the magnitude of the second logiclevel.
 53. The processor-based system of claim 48 wherein thede-emphasized signal overshoots the first signal level for a firstperiod.
 54. The processor-based system of claim 48 wherein thede-emphasized memory signal comprises a de-emphasized address signal.